Here you find a complete list of all the features contained in V3S, including a short description, VHDL and Verilog/SystemVerilog
support, and the corresponding default Visual Studio Shortcut. This list not only contains V3S specific commands and functions,
but also standard features natively supported by Visual Studio which you might find handy.
Coding
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| Feature |
Description |
Default Shortcut
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vhdl
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v/sv
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| Renaming |
Allows semantically correct renaming of signals, variables, functions, entities, etc. |
F2 |
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| Find all references |
Finds all references of a given identifier in the entire project. |
Shift+F12 |
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| Naming rules check |
Checks if the symbols (signals, functions, etc) obey the configured naming conventions |
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| Syntax Highlighting |
Code highlighting according to VHDL 2008 syntax: Keywords, symbols, strings, identifiers, etc. |
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| Semantic Highlighting |
Code highlighting according to semantic analysis: Types, signals, ports, constants, etc. See Syntax Highlighting for details! |
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| Type-time Error Checking |
On-the-fly error checking and highlighting. Output in Visual Studio's Error Output Window. |
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| Code Completion/Autocomplete |
Context sensitive code completion (for defined signals, types, entites, etc.). |
Ctrl+Space |
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| List Symbols |
Shows a list of all defined items (also refer to Code Completion). |
Ctrl+J |
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| Block Selection Keyboard |
Holding Alt+Shift while moving the cursor with the cursor keys uses the very handy block/column-selection mode of Visual Studio. |
Alt+Shift+Cursors |
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| Block Selection Mouse |
Pressing Alt while selecting code with the mouse uses the very handy block/column-selection mode. |
Alt+Mouse |
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| Smart Indentation |
Can be deactivated temporarily with Shift and permanently in Preferences. Automatically sets the indent of new code lines according to formatting rules. |
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| Smart Indentation for Paste |
Can be deactivated temporarily with Shift and permanently in Preferences. Automatically sets the indent of pasted code according to formatting rules. |
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| Increase Indent |
Increases the indent of the currently selected code lines. |
Tab |
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| Decrease Indent |
Decreases the indent of the currently selected code lines. |
Shift+Tab |
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| Quickinfo/Tooltip |
Useful information (e.g., type, default value, location, etc.) of the underlying item are displayed. |
Ctrl+K+I |
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| Expression Evaluator |
Simple constant expressions are automatically evaluated and the result is displayed in the tooltip. Selected expressions are evaluated as well. Also simple string expressions can be resolved. |
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| Number Conversion |
Numbers, Bitstring, Binary String, etc. are converted to decimal, hex, binary formats and displayed as quickinfo. Floats are displayed as IEEE single/double precision floating point number. |
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| Comment Lines |
Comments the selected lines (line commenting). |
Ctrl+K+Ctrl+C |
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| Uncomment Lines |
Uncomments the selected lines (line commenting). |
Ctrl+K+Ctrl+U |
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| Code Snippets (Expansion) |
Opens a list of all available Expansion-Code-Snippets (snippets that insert new code). Select one to insert the respective snippet into the source code. |
Ctrl+K+Ctrl+X |
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| Code Snippets (Surround) |
Opens a list of all available Surround-Code-Snippets (snippets that surround selected code). Make a text selection, then choose a snippet to surround the selected code with the respective snippet. |
Ctrl+K+Ctrl+S |
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| Code Snippets |
Inserts the code snippet with the respective link/shortcut [*]. The following shortcuts are defined:
Expansion Snippets:
- a+Tab: Architecture
- ar+Tab: Assert-Report with severity
- r+Tab: Report with severity
- const+Tab: Constant
- c+Tab: Component (lists available entities)
- ea+Tab: Entity and Architecture
- e+Tab: Entity
- fl+Tab: For-Loop
- fld+Tab: For-Loop (Range: downto)
- flt+Tab: For-Loop (Range: to)
- ig+Tab: if-generate statement
- fg+Tab: for-generate statement
- cg+Tab: case-generate statement
- w+Tab: While-Loop
- f+Tab: Function
- i+Tab: Instance (lists available entites and components)
- if+Tab: If-Then statement
- ife+Tab: If-Then-Else statement
- ifei+Tab: If-Then-Elsif-Else statement
- phb+Tab: Package Head and Body
- ph+Tab: Package Head
- pb+Tab: Package Body (lists available package heads)
- p+Tab: Procedure
- rec+Tab: Record type definition
- sp+Tab: Synchronous Process (lists possible signals for clock and reset)
- ssp+Tab: Simple synchronous process (clock, but no reset)
- ap+Tab: Asynchronous Process
- cs+Tab: Case Statement (lists signal of enumeration type for state-machine implementation)
- o+Tab: (others => '0')
- oo+Tab: (others => '...')
- sig+Tab: Signal declaration of base types: integer, natural, std_logic, boolean, std_logic_vecotor
- sigslv+Tab: Signal declaration for std_logic_vector type
- var+Tab: Variable declaration of base types: integer, natural, std_logic, boolean, std_logic_vecotor
- varslv+Tab: Variable declaration for std_logic_vector type
- sl+Tab: std_logic
- slv+Tab: std_logic_vector()
- u+Tab: unsigned()
- s+Tab: signed()
- tu+Tab: to_unsigned()
- ts+Tab: to_signed()
Surrounding Snippets (xxx is the selected text):
- std_logic_vector(xxx)
- unsigned(xxx)
- signed(xxx)
- to_unsigned(xxx)
- to_signed(xxx)
- if(xxx)
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*+Tab |
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| Code Snippets (Forward) |
When in snippet insertion mode, use TAB to move to the next field (and probably show the suggestions list). |
Tab |
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| Code Snippets (Backward) |
When in snippet insertion mode, use SHIFT+TAB to move to the previous field (and commit the current value for previous, and probably show the suggestions list). |
Shift+Tab |
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| Line Duplication |
When nothing is selected, these shortcuts duplicate the current line. |
Ctrl+C+Ctrl+V |
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| Library View |
Opens a view which shows the current project's library hierarchy. |
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| Hierarchy View |
Opens a view which shows the current project's design hierarchy. |
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| Create Testbench |
Opens a dialog where you can easily create a testbench for an arbitrary entity. |
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| Parameter Help |
Opens a tooltip with parameter help for the current function/procedure/component/entity |
Ctrl+Shift+Space |
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| Code Formatting |
Formats the document or the selection according to your preferences. An (optional) popup-window is shown where settings can be adjusted on the fly |
Ctrl+K+Ctrl+F |
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Navigation
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| Feature |
Description |
Default Shortcut
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vhdl
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v/sv
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| Quick Search |
Shows a dialog to quickly search for project files and global symbols |
Shift+Shift |
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| Find all references |
Finds all references of a given identifier |
Shift+F12 |
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| Navigate Forward |
Move forward to an already visited location |
Ctrl+Shift+- |
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| Navigate Backward |
Move backward to a previously visited location |
Ctrl+- |
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| Code Folding |
Collapse certain code blocks for better overview and navigation efficiency (processes, function, entities, classes, methods, records, instances, ...) |
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| Navigation Bars |
Navigate between design units inside a file, and between code blocks inside a design unit |
Ctrl+F2 |
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| Tuple Highlighting |
Matching of tuples: Brace matching, if-then-elsif-else-end, case-when-end, process-begin-end, etc. matching |
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| Goto Declaration |
Jumps to the declaration of the current item |
Ctrl+F12 |
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| Goto Definition |
Jumps to the definition of the current item (if different from its declaration) |
F12 |
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Project Setup
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| Feature |
Description |
Default Shortcut
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vhdl
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v/sv
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| New Project Wizard |
Starts the V3S New Project Wizard. Within some clicks, you can create an - Empty project
- Sample project
- "Hello World" project
- Import an existing Altera Quartus Project
- Import an existing Xilinx Project (xise, xpr)
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Ctrl+Shift+N |
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| Virtual Folders |
Virtual Folders help to organize your project, especially for files outside the project folder. You can only add files as links into virtual folders. |
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| Linked Folders |
Linked Folders allow you to link physical folders (using absolute path only!). Upon adding a linked folder, V3S can automatically import all contained files for you. |
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| Add New Item |
There are two predefined templates: Add new VHDL Code File, and add new VHDL Library File |
Ctrl+Shift+A |
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| Add Existing Item |
Opens the dialog for adding exsting items to the project. Use "Add as Link" for files outside the project directory |
Shift+Alt+A |
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| Link Files |
You have the option to add files as link to your project only. Choose "Add Existing Item", and click the small arrow next to the "OK"-button, then choose "Add as Link" |
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| Code Statistics per File |
On the HDL files' property page (right-click file in solution explorer, select "Properties"), there are some basic code statistics. The items are - Code lines
- Comment lines
- Empty lines
- Total lines
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| Project-Wide Statistics |
On the project's property page (right-click project in solution explorer, select "Properties"), there are some basic code statistics for all files (except IEEE default libraries) of the project. The items are - Code lines
- Comment lines
- Empty lines
- Total lines
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| File Properties |
Each HDL file has associated file properties specific for V3S. The items are - Content type: Defines the type of the respective code file (Verilog, SystemVerilog, VHDL, Text, ...)
- Library: Defines the VHDL library to which the file belongs. Default is "work"
- Notifcation Level: Defines the types of errors which will be displayed in the Error Output Window
- Parsing Options: Let's you define whether to fully parse the file (which might be slow) or not
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Alt+Return |
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Preferences
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| Feature |
Description |
Default Shortcut
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vhdl
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v/sv
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| Custom Syntax Coloring |
You can define custom colors for all VHDL syntax elements like keywords, symbols, attributes, signals, constants, ... |
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| Color Presets |
I have assembled a number of color presets here for your convenience. There is a special preset for users of the dark theme |
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| Notifications |
Here you can adjust the notification levels for all available code checks |
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| Formatting |
Here you can configure your prefered formatting styles (indenting, newlines, etc.) |
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| Licensing |
Here you can review and setup your license |
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| Naming Conventions |
Here you can import/export your project's naming convention rules |
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| Version |
Here you can review your current version and check for updates |
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| Basics |
General V3S settings |
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| Language Basics |
General Language specific (VHDL/Verilog/SystemVerilog) V3S settings |
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| Edit Templates |
Allows you to edit snippet, testbench, and new file templates |
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Others
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| Feature |
Description |
Default Shortcut
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vhdl
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v/sv
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| Productivity Power Tools |
Productivity Powertools from Microsoft are an excellent and free enhancement for Visual Studio, and they work fine with V3S. I am using them as well, and I wouldn't wanna miss them ever again |
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| Highlight all occurrences |
Also from Microsoft, also free, also very, very useful |
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Overview Video