VHDL and Verilog for Visual Studio

Documentation

V3S | Navigation | Tuple Highlighting


Support

  VHDL
  Verilog

How to Access

Automatic action depending on context (eg, cursor position, settings, window focus, etc.)

Description

Matching of tuples: Brace matching, if-then-elsif-else-end, case-when-end, process-begin-end, etc. matching

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