VHDL and Verilog for Visual Studio


V3S | Coding | Create Testbench



How to Access

V3S main menu
Code-editor (right-click) context menu


Opens a dialog where you can easily create a testbench for an arbitrary entity.


The Create Testbench... feature is one of the most useful features when it comes to eliminating lots of trivial, manual and time-consuming steps. It allows you to create a testbench (i.e. a VHDL file contining a testbench sceleton and a scriptfile to run the testbench in a simulator) for any given entity. V3S thereby performs a lot of work for you:

  • It creates a VHDL file with an instance of your desired DUT (design under test, i.e. entity)
  • It creates the respective signals of the DUT in the testbench
  • It connects all signals of the DUT to signals in the testbench
  • It automatically creates a correct list of use-clauses
  • (Optional) It creates a clock signal with the specified frequency
  • (Optional) It creates a reset signal with the specified duration
  • It creates a (ModelSim) script file to run the testbench (all dependent files are included in the script)
Please refer to the image below for a screenshot of the Create Testbench... dialog. You can activate this dialog in several different places:
  • ...via the V3S main menu
  • ...via the context-menu in a source code window
  • ...via the context-menu in the Hierarchy View (see   Hierarchy View)
  • ...via the context-menu in the Library View (see   Library View)

Create Testbench Dialog

The following table gives a summary of the various elements in the Create Testbench dialog.

  • The combo-box contains a list of all available entites. Just select the entity you want to create a testbench for. Depending on how you invoke the dialog, the default selection probably is already set correctly.
  • Provide a name for the testbench. This must be a valid VHDL identifier as well as a valid filename. The generated VHDL and simulation files will have this name.
Here you define where the generated files will be located. You have the following options:
  • Same Folder: The files will be located in the same folder as the file which contains the entity selected in
  • Subfolder: The files will be created in a subfolder with the specified name. The subfolder will be created in the folder where file which contains the entity-under-test is located.
  • Different Folder: You can also specify an arbitrary location where the created files shall be located in.
Activate the checkbox if you want V3S to automatically create a process in the testbench which generates a clock signal with the specified period. As V3S cannot know (only guess by name) which of the entities port-signals is the clock signal, you need to specify it in the combo-box. Furthermore, you can specify the period of the clock signal. A duty cycle of 50 percent is assumed. Valid time units are ps, ns, us and ms for pico-, nano-, micro- and milliseconds, respectively.
Similar to
you can configure V3S to create a reset signal for you. Again, you have to select the port signal from the combo-box which corresponds to your reset signal. Then you need to specify the duration you want the reset to be asserted. The same time units as in
are valid here.
  • Active Low: By checking this box, the reset signal will be active low.
  • Synchronous deassert: By checking this box, the reset signal will be deasserted synchronously (i.e. with the rising edge of the clock). Otherwise, it will simply be deasserted after the given period of time, regardless of the clock signal.
Select this checkbox to include the generated VHDL file in the current project.
Here you can specify various options concerning the ModelSim script which is generated by V3S. Please notice that some of the options are currently not yet implemented and thus cannot be changed.
  • Use VHDL2008: If checked, the design is compiled with the VHDL2008 switch: vcom -2008 file.vhd
  • Use vmap: If checked, command vmap is used to map all libraries to work. Otherwise, vcom -work file.vhd is used for compilation
  • Create separate file for waveform: If checked, a separate file is created for adding signals to the waveform window.
  • Hierarchy depth: Defines the depth of the instance-hierarchy for signals that are to be added to the testbench.
    • If set to 0, only the testbenches signals are added to the waveform window
    • If set to 1, the testbenches signals, and the signals of the unit-under-test are added to the waveform window
    • If set to 2, in addition to above, all signals of all instances found directly in the unit-under-test are added to the waveform window
    • ...

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