VHDL and Verilog for Visual Studio

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V3S | Coding | Code Snippets


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  Verilog

How to Access

Default Shortcut: *+Tab
Action triggered by shortcut

Description

Inserts the code snippet with the respective link/shortcut [*]. The following shortcuts are defined:
Expansion Snippets:

  • a+Tab: Architecture
  • ar+Tab: Assert-Report with severity
  • r+Tab: Report with severity
  • const+Tab: Constant
  • c+Tab: Component (lists available entities)
  • ea+Tab: Entity and Architecture
  • e+Tab: Entity
  • fl+Tab: For-Loop
  • fld+Tab: For-Loop (Range: downto)
  • flt+Tab: For-Loop (Range: to)
  • w+Tab: While-Loop
  • f+Tab: Function
  • i+Tab: Instance (lists available entites and components)
  • if+Tab: If-Then statement
  • ife+Tab: If-Then-Else statement
  • ifei+Tab: If-Then-Elsif-Else statement
  • phb+Tab: Package Head and Body
  • ph+Tab: Package Head
  • pb+Tab: Package Body (lists available package heads)
  • p+Tab: Procedure
  • rec+Tab: Record type definition
  • sp+Tab: Synchronous Process (lists possible signals for clock and reset)
  • ssp+Tab: Simple synchronous process (clock, but no reset)
  • ap+Tab: Asynchronous Process
  • cs+Tab: Case Statement (lists signal of enumeration type for state-machine implementation)
  • o+Tab: (others => '0')
  • oo+Tab: (others => '...')
  • sig+Tab: Signal declaration of base types: integer, natural, std_logic, boolean, std_logic_vecotor
  • sigslv+Tab: Signal declaration for std_logic_vector type
  • var+Tab: Variable declaration of base types: integer, natural, std_logic, boolean, std_logic_vecotor
  • varslv+Tab: Variable declaration for std_logic_vector type
  • sl+Tab: std_logic
  • slv+Tab: std_logic_vector()
  • u+Tab: unsigned()
  • s+Tab: signed()
  • tu+Tab: to_unsigned()
  • ts+Tab: to_signed()
Surrounding Snippets (xxx is the selected text):
  • std_logic_vector(xxx)
  • unsigned(xxx)
  • signed(xxx)
  • to_unsigned(xxx)
  • to_signed(xxx)
  • if(xxx)

Documentation

Snippets can be inserted by typing their shortcut and then pressing the Tab key. A list of available snippets can be displayed by using either of the following:

  • Ctrl+K+Ctrl+X (Expansion Snippets)
  • Ctrl+K+Ctrl+S (Surrounding Snippets)
  • Ctrl+Space (only if snippets are enabled to show for Code-Completion, see Preferences-  Basics)

The following table lists all snippets that have custom snippet fields. V3S provides lists of possible candidates for those fields from which you can choose. It is also possible to write any value to these fields in case the provided lists do not contain the correct entry.

package head name: The name of the package
package body name: The name of the package
procedure name: The name of the procedure]
synchronous process label: The label of the process
clock: The clock signal used as clock for the synchronous process. A list with signals containing clock, clk, ck, is provided.
reset: The (asynchronous) reset signal used as reset to the synchronous process. A list with signals containing reset,rst,clear,... is provided.
asynchronous process label: The label of the process
signed -
simple process label: The label of the process
clock: The clock signal used as clock for the synchronous process. A list with signals containing clock, clk, ck, is provided.
std_logic -
std_logic_vector -
to_signed -
to_unsigned -
unsigned -
package head + body name: The name of the package
others -
others (general) value: The value of the others-assignment
entity name: The name of the entity, by default the filename
component name: The name of the component. A list containing defined entites is provided. Upon selection of an entity, the component's body is automatically filled with the generics/ports of the respective entity.
case name: The name of the symbol for the case statement. A list of "state signals" (signals which have an enumeration-type) is provided. Upon selection of a state-signal, the case-statement's body is automatically filled with all the choices of the respective enumeration type.
instance label: The label of the instance
instance: The comonent/entity that is to be instantiated. A list of available components/entities is displayed. Upon selection of an entity/component, the instance-body is automatically filled with the respective generic/port maps using default signal names on the right side of the association.
function name: The name of the function
return: The return value of the function. A List of defined types is provided.
entity and architecture entity: The name of the entity
arch: The name of the architecture
architecture entity: The name of the entity. Alist of available entities is provided
arch: The name of the architecture
assert condition: Condition of the assert-statement
message: Message to be reported on assertion
severity: Severity level of reported message (note, warning, error, failure)
report message: Message to be reported
severity: Severity level of reported message (note, warning, error, failure)
constant name: Name of the constant
type: Type of the constant, one of the base types (integer, natural, boolean, std_logic, std_logic_vector)
default: Severity level of reported message
for-loop -
for-loop (downto) -
for-loop (to) -
while-loop (to) -
if-then condition: Condition of the if-statement
if-then-else -
if-then-elsif-else condition1: Condition of the if-statement
condition2: Condition of the elsif-statement
record name: Name of the record-type
signal name: Name of the signal
type: Type of the signal, one of the base types (integer, natural, boolean, std_logic, std_logic_vector)
signal (std_logic_vector) name: Name of the signal
range: Range of the std_logic_vector array
variable name: Name of the variable
type: Type of the variable, one of the base types (integer, natural, boolean, std_logic, std_logic_vector)
variable (std_logic_vector) name: Name of the variable
range: Range of the std_logic_vector array
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