VHDL, Verilog, SystemVerilog for Visual Studio


V3S | Coding | Smart Indentation



How to Access

Automatic action depending on context (eg, cursor position, settings, window focus, etc.)


Can be deactivated temporarily with Shift and permanently in   Preferences. Automatically sets the indent of new code lines according to formatting rules.


While typing, V3S automatically handles the indentation of your source code. For example, after typing something like if condition then and hitting Enter, V3S automatically adds one level of indentation (using the specified amount of spaces or tabs, depending on your preferences) for the next line of code. You can just continue typing. Likewise, if you tpye else or end if you will notice that V3S automatically dedents the code accordingly.

To activate/deactivate this feature, navigate to Preferences|Common|Basics|Integration.

When activated, you can also deactivate this feature temporarily by pressing Shift. While Shift is pressed, Smart Indentation will not be applied to the current line of code.

Activate/Deactivate Smart Indentation

You can specify how you want your code formatted in the V3S Preferences dialog. There are a couple of settings that directly influence the behavior of smart indentation. They can be found in Preferences|VHDL|Code Formatting|Indentation. Take a look at the following image and table to learn about the configuration options for smart indentation.

Indentation/Code Formatting options

Indent 'report' and 'severity' in assert statements (if written in new line)
assert true
  report "Message"
  severity failure; 
Indent 'when'choices in select statements
case state is
  when IDLE =>
  when SEND =>
  when DATA =>
end case; 
Indent declaration-area (between 'is' and 'begin' keyword)
architecture rtl of synchronizer is
  signal sync_data1: std_logic_vector(DATAWIDTH - 1 downto 0);
  signal sync_data2: std_logic_vector(DATAWIDTH - 1 downto 0);
  signal data      : std_logic_vector(DATAWIDTH - 1 downto 0);
Indent port/generic maps for component instances
spi_inst: spi
  generic map (
    SPI_OWN_ADDRESS_G => "101"
  port map (
    clk_i => clk,
    rst_i => rst
Indent 'use' declarations after 'library' declaration
library ieee;
  use ieee.std_logic_1164.all;
  use ieee.numeric_std.all; 
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