VHDL and Verilog for Visual Studio

Documentation

V3S | Coding | Type-time Error Checking


Support

  VHDL
  Verilog

How to Access

Automatic action depending on context (eg, cursor position, settings, window focus, etc.)

Description

On-the-fly error checking and highlighting. Output in Visual Studio's Error Output Window.

Documentation

For VHDL, there are several errors that are checked on-the-fly. Thus common mistakes can be corrected before actually starting the simulator or synthesis tool, which saves a significant amount of time and frustration. There are several options related to error checking:
  • V3S|Preferences...|Common|Basics: Under Integration you can define how many errors to display at most in the error-list toolwindow.
  • For each file, you can define the Notifcation Level in the file's properties window. Please refer to   File Properties for further details.
  • V3S|Preferences...|VHDL|Code Checks: See below for details; Here you can globally enable/disable error-checks, and assign severities for all supported errors.
V3S VHDL Code Checks Dialog


Severity Levels
None The Error is ignored. It's neither displayed in the error-list window, nor highlighted in the code-editor window
Info The Error is treated as information only. Usually, depending on Visual Studio Settings, information entries are not highlighted in the code-editor window. However, they are displayed as in the error-list window.
Warning The Error is treated as warning. Usually it is highlighted with a blue squiggly line in the code-editor window, and of course there is a warning entry in the error-list window.
Error Usually it is highlighted with a red squiggly line in the code-editor window, and of course there is an error entry in the error-list window.
Fatal This is the same as Error. It has been added in case of future needs.

Errors Checked while Typing
Syntax Errors Of course, any syntax errors are checked and displayed. The VHDL standard which is used for parsing is VHDL2008. Please notice that files with syntax errors may not be parsed correctly, i.e. the symbols defined may not be recognized by V3S until the syntax errors are resolved.
Variable/Signal assignment operator mismatch If a variable is assigned to using
<=
rather than
:=
. Similaly - but the other way around - for signals.
Symbol already exists in the current scope A symbol was defined twice in the same scope. The error-message shows the location of the original defintion.
Symbol is undefined A symbol (e.g., signal name, variable name, etc) is undefine, i.e. it is not declared.
Symbol is READ-only and cannot be modified Some signals cannot be written to. For example, input signals of entites, input signals of subroutines, etc. The error is issued if an assignment is made to such a symbol.
The target of the assignment is invalid (no L-value) This error is issued if one tries to assign a value to something that is not assignable, e.g. functions, packages, etc.
Symbol is defined, but never written to This check is not yet supported.
Symbol cannot be used in pure function Pure function cannot call impure functions, or use signals/variables which are defined outside of the function itself
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