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V3S | Coding | Naming rules check



How to Access

Automatic action depending on context (eg, cursor position, settings, window focus, etc.)


Checks if the symbols (signals, functions, etc) obey the configured naming conventions


V3S has the ability to check your code against self-defined naming conventions. The easiest way to define your own naming rules is to export the current settings (even if there are none - a dummy file containing all necessary entries is created), modify them, and import them back into V3S. But first things first, let's look at the preferences window found at V3S|Preferences....

Select Naming Conventions in the V3S preferences window to show the respective settings.
You must explicitly enable naming checks by checking this checkbox. Notice that you can also enable/disable naming checks on a per-file basis in the respective file's   File Properties. Also notice that you can define the message severity for naming rule violations. This affects the Error-List toolwindow and the type of underlining (red for errors, blue for warnings) in the code window.
Use this button to export the current settings. If you have not yet defined custom settings, a stub file is generated which contains all available settings, documentation, and examples. You should easily be able to modify the file based on the information provided within the file itself.
After modifying the naming rules, import the file. Notice that you have to explicitly import naming rules files as they are not automatically re-imported upon modification. If importing the new settings was successful, you can see them in the settings area
This is the settings area where V3S displays the current set of naming conventions. This area is empty if there are no custom rules defined.
Once you are happy with the configuration, apply the settings.

If you take a look at the exported settings file, you can see that the file is divided into four sections.
  • V3sNamingTypes
    : In this section you can define affixes for predefined types as well as your own types. Just add a line to the file with the name of your custom type, and assign the desired affix to it. For example, if you want signals of type integer to be suffixed with
    , this is the place to assign the character.
  • V3sNamingTypeSpecs
    : In this section you can define affixes for signals of different kinds of types. In VHDL there are access types, enum types, records, arrays, file types, unit types and range types. For example, if you define a signal of a type that is itself a record, the affix defined here can be used.
  • V3sNamingDirections
    : Here you can define affixes for the direction of a signal.
  • V3sNamingSymbols
    : This is the central section where you actually define how your naming conventions look like. Here you use the definitions of the other sections to compose naming rules for all kinds of symbols. Take a look at the table below to learn how to reference the defined affixes of the other sections.
If you want to disable a specific setting, just delete the respective line or remove the text right of the
character. All missing (or empty) entries will be ignored when checking the naming conventions. The following table lists the various variables you can use to reference any of the defined affixes. Also look at the examples to get a better understanding of how things work.
Symbol-Name Description
The affix/name must be all-lowercase
Notice the first capital letter. The affix/name starts with a capital letter, followed by all-lowercase letters.
The affix/name must be all-uppercase
Notice the exclamation mark instead of the percentage-character. The affix/name must match exactly as defined by the user. Useful for using CamelCase or other more complex combinations of upper/lowercase characters.
Don't care at all for uppoer/lowercase conventions.

It's always easiest to just take a look at some examples to learn how things work. Assume the following (striped-down) configuration file. Notice that I removed all the comments and all unused entries from the file to improve readability. Just follow the steps above to export the file to obtain a fully featured version of the V3S naming convention settings.

Naming Rules Configuration:

boolean           = b
boolean_vector    = bv
integer           = i
integer_vector    = iv
std_logic         = sl
std_logic_vector  = slv

enum   = e  
record = r  
array  = a  
file   = f  

in      = i 
out     = o 
inout   = io

AccessType             = !Name_ptrt
ArrayType              = !Name_at
EnumType               = !Name_et
RecordType             = !Name_rt
Type                   = !Name_%type_t
EntityPortSignal       = !Name_%dir
Signal                 = !Name_s
Variable               = !Name_v
Constant               = %NAME_C
Generic                = %NAME_G
ProcessLabel           = !Name_p
GenerateLabel          = !Name_gen
InstanceLabel          = !Name_inst
Function               = !Name_f
Enum                   = %NAME_E

Sample VHDL file:

library IEEE;
  use IEEE.std_logic_1164.all;
  use IEEE.numeric_std.all;

entity naming_ent is                                           -- Entity: Match
  generic (                                                    
    WIDTH_G  : integer;                                        -- Generic: Match
    Height_G : integer                                         -- Generic: Mismatch, should be "HEIGHT_G"
  port (                                                       
    clk_i : in  std_logic;                                     -- EntityPortSignal: Match
    dmy_o : inout std_logic;                                   -- EntityPortSignal: Mismatch, should be "dmy_io"
    data_o : out std_logic                                     -- EntityPortSignal: Match
end entity;                                                    
architecture rtl of naming_ent is                              -- Architecture: Mismatch, should be "rtl_arch"
  constant MY_CONST_C: integer := 5;                           -- Constant: Match
  type accessType_ptrt is access std_logic_vector(1 downto 0); -- AccessType: Match
  type arrayType_a is array(natural range <>) of std_logic;    -- ArrayType: Mismatch, should be "arrayType_at"
  type enumType_et is (                                        -- EnumType: Match
    ENUM1_E,                                                   -- Enum: Match
    ENUM2,                                                     -- Enum: Mismatch, should be ENUM2_E
    enum3_E);                                                  -- Enum: Mismatch, should be ENUM3_E
  type myType_rt is record                                     -- RecordType: Match
    iField: integer;                                           -- RecordField: Match
    slField: std_logic;                                        -- RecordField: Match
    bField1: std_logic;                                        -- RecordField: Mismatch, should be "slField1"
  end record;
  signal mySig1_mt_s: myType_rt;                               -- Signal: Match
  signal mySig2_sl_s: std_logic;                               -- Signal: Match
  signal mySig3_i: integer;                                    -- Signal: Mismatch, should be "mySig3_i_s"
  myProcessLabel_p: process is                                 -- ProcessLabel: Match
    variable myVar1_av: arrayType_a(1 to 2);                   -- Variable: Match
    variable myVar2_rv: myType_rt;                             -- Variable: Match
    variable myVar3_ev: enumType_et;                           -- Variable: Match
  end process;
end architecture;

Entries in Error-List-Toolwindow

The Error-List toolwindow shows a list of symbols that does not conform to the configured naming conventions. As usual, a double-click on an item directly jumps to the respective location. Notice that you can configure the severity of the displayed messages in the V3S preferences (see above for details).

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