VHDL and Verilog for Visual Studio

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V3S | Coding | Renaming


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  VHDL
  Verilog

How to Access

Default Shortcut: F2
Action triggered by shortcut
V3S main menu

Description

Allows efficient renaming of signals, variables, functions, entities, etc.

Documentation

Remarks
  • When renaming an entity, all references are renamed:
    • Architectures
    • Component declarations of this entity
    • Instances of this entity (either via component or directly)
  • When renaming port signals of entities/components, all references are renamed:
    • All port-map/generic-map declarations for entities/components
    • All component declarations of this entity
    • All usages of the symbol in the corresponding architecture
  • When renaming functions or procedures, all overloaded subroutines are renamed as well.
  • If the current file contains syntax errors, renaming is not possible
  • Always backup your work before performing refactorization
  • Always review the changes in the preview window before applying them

Rename Window



1
Here you can enter the new name of the symbol. Notice that it must be a valid identifier.
2
Shows the location in form of the design's hierarchy. In this example, the symbol GetFrequency is located in library clocking_lib, package clocking_lib in file clocking_lib.vhd
3
If checked, pressing [Enter] or clicking OK/Next (grayed out in this example) shows the "Review Changes" page rather than applying the changes immediately. You should always review the changes beforehand.
4
If checked, all changed files are kept open and unsaved. This way you can take a look at the changes once more before actually saving them.
5
Renaming might not work properly if affected files contain syntax errors (as in this example). You also get a respective message at the bottom (item
7
). You can only proceed if you explicitly check this checkbox in order to confirm that you are aware of the potential problems regarding syntax errors.
6
If there are any special remarks that might me of interest for you, they are displayed here. In this example V3S informs you that renaming a function also renames all overloads of this function.
7
Status and information area. In case of errors/warnings, they are shown here. Otherwise, a short summary about the planned renaming-action is shown.



1
This field shows a list of all files that will be affected by the renaming operation. Just select a file (single-click) to get a more detailed overview of the changes in field
2
.
2
Provides a list of changes for the selected file in
1
. You can double-click each entry to jump to the respective source-code location in the text-editor in order to review the intended changes.
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